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19-4688; Rev 2; 7/09
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
General Description
The DS2775-DS2778 report available capacity for rechargeable lithium-ion (Li+) and Li+ polymer (Li-Poly) batteries in mAh and as a percentage of full. Safe operation is ensured by the integrated Li+ protector. The DS2776/DS2778 support SHA-1-based challengeresponse authentication in addition to all other DS2775/ DS2777 features. Precision measurements of voltage, temperature, and current, along with a cell characteristics table and application parameters, are used for capacity estimation calculations. The capacity registers report a conservative estimate of the amount of charge that can be removed given the current temperature, discharge rate, stored charge, and application parameters. The DS2775-DS2778 operate from +4.0V to +9.2V for direct integration into battery packs with two Li+ or LiPoly cells. In addition to nonvolatile storage for cell compensation and application parameters, the DS2775-DS2778 offer 16 bytes of EEPROM for use by the host system and/or pack manufacturer to store battery lot and date tracking information. The EEPROM can also be used for nonvolatile storage of system and/or battery usage statistics. A Maxim 1-Wire (R) (DS2775/DS2776) or 2-wire (DS2777/DS2778) interface provides serial communication to access measurement and capacity data registers, control registers, and user memory. The DS2776/DS2778 use the SHA-1 hash algorithm in a challenge-response pack authentication protocol for battery-pack verification.
Features
High-Side nFET Drivers and Protection Circuitry Precision Voltage, Temperature, and Current Measurement System Cell-Capacity Estimation from Coulomb Count, Discharge Rate, Temperature, and Cell Characteristics Estimates Cell Aging Between Learn Cycles Uses Low-Cost Sense Resistor Allows Calibration of Gain and Temperature Coefficient Programmable Thresholds for Overvoltage and Overcurrent Pack Authentication Using SHA-1 Algorithm (DS2776/DS2778) 32-Byte Parameter EEPROM 16-Byte User EEPROM Maxim 1-Wire Interface with 64-Bit Unique ID (DS2775/DS2776) 2-Wire Interface with 64-Bit Unique ID (DS2777/DS2778) 3mm x 5mm, 14-pin TDFN Lead-Free Package
DS2775/DS2776/DS2777/DS2778
Ordering Information
PART DS2775G+ DS2775G+T&R DS2776G+ DS776G+T&R DS2777G+ DS2777G+T&R DS2778G+ DS2778G+T&R PIN-PACKAGE 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP* 14 TDFN-EP* TOP MARK D2775 D2775 D2776 D2776 D2777 D2777 D2778 D2778
Applications
Low-Cost Notebooks UMPCs DSLR Cameras Video Cameras Commercial and Military Radios Portable Medical Equipment
Selector Guide and Pin Configuration appear at end of data sheet.
Note: All devices are specified over the -20C to +70C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
ABSOLUTE MAXIMUM RATINGS
Voltage Range on PLS, CP, CC, DC Pins Relative to VSS .....................................................-0.3V to +18V Voltage Range on VDD, VIN1, VIN2, SRC Pins Relative to VSS ....................................................-0.3V to +9.2V Voltage Range on All Other Pins Relative to VSS ..-0.3V to +6.0V Continuous Sink Current, PIO, DQ......................................20mA Continuous Sink Current, CC, DC.......................................10mA Operating Temperature Range ...........................-20C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +4.0V to +9.2V, TA = -20C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL IDD0 Supply Current IDD1 IDD2 Temperature Accuracy T ERR 2.0 VIN1 4.6, 2.0 0C TA +50C Voltage Accuracy 2.0 VIN1 4.6, 2.0 TA = +25C 2.0 Input Resistance (VIN1, VIN2) Current Resolution Current Full Scale Current Gain Error Current Offset Accumulated Current Offset Time-Base Error CP Output Voltage (VCP - VSRC) CP Startup Time Output High: CC, DC Output Low: CC Output Low: DC DQ, PIO Voltage Range DQ, PIO, SDA, SCL Input Logic-High DQ, PIO, SDA, SCL Input Logic-Low OVD Input Logic-High OVD Input Logic-Low VIH VIL VIH VIL VBAT - 0.2 VSS + 0.2 ILSB IFS I GERR I OERR qOERR t ERR VGS t SCP VOHCP VOLCC VOLDC 0C 0C 0C TA TA TA +70C (Note 1) +70C (Note 1) +50C -51.2 -1 -9.375 -255 -2 -3 I OUT = 0.9A CE = 0, DE = 0, CCP = 0.1F, active mode I OH = 100A (Note 2) I OL = 100A I OL = 100A -0.3 1.5 0.6 VCP - 0.4 VSRC + 0.1 VSRC + 0.1 +5.5 4.4 4.7 VIN1 4.6, 2.0 (VIN2 - VIN1) (VIN2 - VIN1) (VIN2 - VIN1) 4.6, 4.6, 4.6 CONDITIONS Sleep mode, TA Active mode Active mode during SHA-1 computation -3 -35 -22 -50 15 1.56 +51.2 +1 9.375 0 +2 +3 5 200 +50C Sleep mode, TA > +50C 80 120 MIN TYP 3 MAX 5 10 135 300 +3 +35 22 +50 M V mV % FS Vh Vh/Day % V ms V V V V V V V V mV C A UNITS
2
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +4.0V to +9.2V, TA = -20C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DQ, PIO, SDA Output Logic-Low DQ, PIO Pullup Current DQ, PIO, SDA, SCL Pulldown Current DQ Input Capacitance DQ Sleep Timeout PIO, DQ Wake Debounce SYMBOL VOL I PU I PD CDQ t SLEEP tWDB DQ < VIL Sleep mode 2 100 I OL = 4mA Sleep mode, VPIN = (VDD - 0.4V) Active mode, V PIN = 0.4V 30 30 100 100 50 9 CONDITIONS MIN TYP MAX 0.4 200 200 UNITS V nA nA pF s ms
DS2775/DS2776/DS2777/DS2778
SHA-1 COMPUTATION TIMING (DS2776/DS2778 ONLY)
(VDD = +4.0V to +9.2V, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Computation Time SYMBOL tCOMP CONDITIONS MIN TYP MAX 30 UNITS ms
ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT
(VDD = +4.0V to +9.2V, TA = 0C to +50C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Overvoltage Detect Charge-Enable Voltage Undervoltage Detect Overcurrent Detect: Charge Overcurrent Detect: Discharge Short-Circuit Current Detect Overvoltage Delay Undervoltage Delay Overcurrent Delay Short-Circuit Delay Charger-Detect Hysteresis Test Threshold Test Current PLS Pulldown Current Recovery Current SYMBOL VOV VCE VUV VCOC VDOC VSC tOVD tUVD tOCD tSCD VCD VTP ITST IPPD IRC VUV condition COC, DOC condition DOC condition COC condition Sleep mode VUV condition, max: VPLS = 15V, VDD = 1.4V; min: VPLS = 4.2V, VDD = 2V 0.4 20 -45 200 3.3 CONDITIONS VOV = 1110111b VOV = 1100011b Relative to V OV Programmable in Control register 0x60h, UV[1:0] = 10 OC = 11b OC = 00b OC = 11b OC = 00b SC =1b SC = 0b (Note 3) (Note 3) 2.415 -60 -12.5 80 25 240 120 600 600 8 80 10 120 50 1.0 40 -60 400 8 1.2 80 -95 630 13 MIN 4.438 4.242 TYP 4.473 4.277 -100 2.450 -75 -25 100 38 300 150 2.485 -90 -38 120 50 360 180 1400 1400 12 160 MAX 4.508 4.312 UNITS V mV V mV mV mV ms ms ms s mV V A A mA
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
EEPROM RELIABILITY SPECIFICATION
(VDD = +4.0V to +9.2V, TA = -20C to +70C, unless otherwise noted.)
PARAMETER EEPROM Copy Time EEPROM Copy Endurance SYMBOL tEEC NEEC TA = +50C 50,000 CONDITIONS MIN TYP MAX 10 UNITS ms Cycles
ELECTRICAL CHARACTERISTICS: 1-Wire INTERFACE, STANDARD (DS2775/DS2776 ONLY)
(VDD = +4.0V to +9.2V, TA = -20C to +70C.)
PARAMETER Time Slot Recovery Time Write-Zero Low Time Write-One Low Time Read Data Valid Reset Time High Reset Time Low Presence-Detect High Presence-Detect Low SYMBOL t SLOT tREC tLOW0 tLOW1 tRDV tRSTH tRSTL t PDH t PDL 480 480 15 60 960 60 240 CONDITIONS MIN 60 1 60 1 120 15 15 TYP MAX 120 UNITS s s s s s s s s s
ELECTRICAL CHARACTERISTICS: 1-Wire INTERFACE, OVERDRIVE (DS2775/DS2776 ONLY)
(VDD = +4.0V to +9.2V, TA = -20C to +70C.)
PARAMETER Time Slot Recovery Time Write-Zero Low Time Write-One Low Time Read Data Valid Reset Time High Reset Time Low Presence-Detect High Presence-Detect Low SYMBOL t SLOT tREC tLOW0 tLOW1 tRDV tRSTH tRSTL t PDH t PDL 48 48 2 8 80 6 24 CONDITIONS MIN 6 1 6 1 16 2 2 TYP MAX 16 UNITS s s s s s s s s s
4
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (DS2777/DS2778 ONLY)
(VDD = +4.0V to +9.2V, TA = -20C to +70C.)
PARAMETER SCL Clock Frequency Bus-Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition Low Period of SCL Clock High Period of SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for STOP Condition Spike Pulse Widths Suppressed by Input Filter Capacitive Load for Each Bus Line SCL, SDA Input Capacitance SYMBOL f SCL tBUF tHD:STA tLOW tHIGH t SU:STA tHD:DAT t SU:DAT tR tF t SU:STO t SP CB CBIN (Note 8) (Note 9) (Notes 6, 7) (Note 6) (Note 5) (Note 4) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 0 50 400 60 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s s ns ns ns s ns pF pF
DS2775/DS2776/DS2777/DS2778
Note 1: Accumulation bias and offset bias registers set to 00h. NBEN bit set to 0. Note 2: Measurement made with VSRC = +8V, VGS driven with external +4.5V supply. Note 3: Overvoltage (OV) and undervoltage (UV) delays (tOVD, tUVD) are reduced to zero seconds if the OV or UV condition is detected within 100ms of entering active mode. Note 4: Timing must be fast enough to prevent the DS2777/DS2778 from entering sleep mode due to bus low for period > tSLEEP. Note 5: fSCL must meet the minimum clock low time plus the rise/fall times. Note 6: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 7: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. Note 9: CB is total capacitance of one bus line in pF.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
DISCHARGE-OVERCURRENT PROTECTION DELAY
DS2775/6/7/8 toc01
CC FET GATE TURN-OFF DURING CHARGE-OVERCURRENT EVENT
DS2775/6/7/8 toc02
2V/div 0V 2V/div 0V 1V/div 0V 20mV/div 0V 0 2 4 6 VGS VSNS 25m SENSE RESISTOR WITH DISCHARGEOVERCURRENT 8 10 12 14 16 18 20 THRESHOLD = 38mV TIME (ms) DC FET SOURCE DC FET GATE
2V/div 0V 2V/div 0V 1V/div 0V 0V 20mV/div 0 5
CC FET GATE CC FET SOURCE
VGS CC FET VSNS 25m SENSE RESISTOR WITH CHARGEOVERCURRENT 10 15 20 25 30 35 40 45 50 THRESHOLD = 25mV TIME (s)
DC FET GATE TURN-OFF DURING SHORT-CIRCUIT EVENT
DS2775/6/7/8 toc03
SHORT-CIRCUIT PROTECTION DELAY
DS2775/6/7/8 toc04
2V/div 0V 2V/div 0V 1V/div 0V 50mV/div 0V 0 2 4 6 8 10 12 14 16 18 20 VGS DC FET VSNS 25m SENSE RESISTOR WITH SHORT-CIRCUIT THRESHOLD = 150mV TIME (s) DC FET SOURCE DC FET GATE
2V/div 0V 2V/div 0V 1V/div 0V 100mV/div 0V 0 VGS DC FET VSNS 25m SENSE RESISTOR WITH SHORT-CIRCUIT THRESHOLD = 150mV 20 40 60 80 100 120 140 160 180 200 TIME (s) DC FET SOURCE DC FET GATE
VOLTAGE MEASUREMENT ACCURACY
18 16 ACCURACY (mV) 14 12 10 8 6 4 2 0 0 1 2 VINX (V) 3 4
2 0 -2
DS2775/6/7/8 toc05
CHARGE-PUMP STARTUP EXITING SLEEP MODE (VDD = 8V NO LOAD ON PK+)
8 7 6
VOLTAGE (V)
DS2775/6/7/8 toc06
20
12.6V
-20C +70C +25C
5 4 3 2.75V
0
10 20 30 40 50 60 70 80 90 100 TIME (ms)
6
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
CURRENT MEASUREMENT ACCURACY
DS2775/6/7/8 toc07
DS2775/DS2776/DS2777/DS2778
IRC vs. VDD
DS2775/6/7/8 toc08
CURRENT MEASUREMENT OFFSET vs. TEMPERATURE
DS2775/6/7/8 toc09
125
7 1k RESISTOR FROM PLS TO PK+ 6 5 4 3 2
2 1 0 LSB (1.5625V) -1 -2 -3 -4 -5
75 ACCURACY (V)
-20C +25C
-25 +70C -75
IRC (mA) -0.032 -0.012 0.008 0.028 0.048
25
1 -125 -0.052 0 0 1 2 3 VDD (V) 4 5 6 VSNS (mV)
-20
0
20
40
60
TEMPERATURE (C)
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- NAME CC VDD DC VIN2 VIN1 VB VSS SNS PIO PLS SDA/DQ SCL/OVD SRC CP EP Charge Control. Charge FET control output. Chip-Supply Input. Bypass with 0.1F to VSS. Discharge Control. Discharge FET control output. Battery Voltage Sense Input 2. Connect to highest voltage potential positive cell terminal through decoupling network. Battery Voltage Sense Input 1. Connect to lowest voltage potential positive cell terminal through decoupling network. Regulated Operating Voltage. Bypass with 0.1F to VSS. Device Ground. Chip ground and battery-side sense resistor input. Sense Resistor Connection. Pack-side sense resistor sense input. Programmable I/O. Can be configured as wake input. Pack Plus Terminal Sense Input. Used to detect the removal of short-circuit, discharge overcurrent, and charge overcurrent conditions. Data Input/Output. Serial data I/O, includes weak pulldown to detect system disconnect and can be configured as wake input for 1-Wire devices. Serial Clock Input/Overdrive Select. Communication clock for 2-wire devices/overdrive select pin for 1-Wire devices. Protection MOSFET Source Connection. Used as a reference for the charge pump. Charge Pump Output. Generates gate drive voltage for protection FETs. Bypass with 0.47F to SRC. Exposed Pad. Connect to ground or no connection. FUNCTION
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Block Diagram
VOLTAGE POWER-MODE CONTROL PLS Li+ PROTECTOR CURRENT 15-BIT + SIGN ADC 10-BIT + SIGN ADC/MUX TEMPERATURE
VIN2 VIN1
SNS
FuelPackTM ALGORITHM CC DC FET DRIVERS
PRECISION ANALOG OSCILLATOR
VREF
VSS
CP VDD CHARGE PUMP
CONTROL AND STATUS REGISTERS PIO LOGIC 32-BYTE PARAMETER EEPROM 16-BYTE USER EEPROM DS2775-DS2778 VB INTERNAL
VOLTAGE REGULATOR VB
COMMUNICATION INTERFACE
PIN DRIVERS AND POWER SWITCH CONTROL
SDA/DQ SCL/OVD PIO
FuelPack is a trademark of Maxim Integrated Products, Inc.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
DS2775/DS2776 Typical Application Circuit
DS2775/DS2776/DS2777/DS2778
PK+
1k
1k
1k
150
1k
150 DATA
PLS DQ PIO
CC
SRC
DC
VDD VIN2 1k VIN1 CP 0.47F 0.1F SRC
DS2775 DS2776 SNS RSNS
5.1V 0.1F
VB
VSS OVD
PK-
DS2777/DS2778 Typical Application Circuit
PK+
1k
1k
1k
150
1k
150 SDA SCL 150 5.1V 5.1V 0.1F
PLS SDA SCL PIO VB
CC
SRC
DC
VDD VIN2 1k VIN1 CP 0.47F 0.1F SRC
DS2777 DS2778 SNS RSNS VSS
PK-
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Detailed Description
The DS2775-DS2778 function as an accurate fuel gauge, Li+ protector, and SHA-1-based authentication token (SHA-1-based authentication available only on the DS2776/DS2778). The fuel gauge provides accurate estimates of remaining capacity and reports timely voltage, temperature, and current measurement data. Capacity estimates are calculated from a piecewise linear model of the battery performance over load and temperature along with system parameters for charge and end-of-discharge conditions. The algorithm parameters are user programmable and can be modified within the pack. Critical capacity and aging data are periodically saved to EEPROM in case of short-circuit or deep-depletion events. The Li+ protection function ensures safe, high-performance operation. nFET protection switches are driven with a charge pump that maintains gate drive as the cell voltage decreases. The high-side topology preserves the ground path for serial communication while eliminating the parasitic charge path formed when the fuel-gauge IC is located inside the protection FETs in a low-side configuration. The thresholds for overvoltage, undervoltage, overcurrent, and short-circuit current are user programmable for customization to each cell and application. The 32-bit-wide SHA-1 engine with 64-bit secret and 64-bit challenge words resists brute force and other attacks with financial-level HMAC security. The challenge of managing secrets in the supply chain is addressed with the compute next secret feature. The unique serial number or ROM ID can be used to assign a unique secret to each battery. serve power by disabling measurement and capacity estimation functions, but preserve register contents. Gate drive to the protection FETs is disabled in sleep; the SHA-1 authentication feature is not operational. The IC enters sleep mode under two different conditions: bus low and undervoltage. An enable bit makes entry into sleep optional for each condition. Sleep mode is not entered if a charger is connected (VPLS > VDD + VCD) or if a charge current of 1.6mV/RSNS measured from SNS to VSS. The DS2775-DS2778 exit sleep mode upon charger connection or a low-to-high transition on any communication line. The bus-low condition, where all communication lines are low for tSLEEP, indicates pack removal or system shutdown in which the bus pullup voltage, V PULLUP, is not present. The power mode (PMOD) bit must be set to enter sleep when a bus-low condition occurs. After the DS2775-DS2778 enter sleep due to a bus-low condition, it is assumed that no charge or discharge current flows and that coulomb counting is unnecessary. The second condition to enter sleep is an undervoltage condition, which reduces battery drain due to the DS2775-DS2778 supply current and prevents overdischarging the cell. The DS2775-DS2778 transition to sleep mode if the VIN1 or VIN2 voltage is less than VUV and the undervoltage enable (UVEN) bit is set. The communication bus must be in a static state, that is, with DQ (SDA and SCL for 2-wire) either high or low for t SLEEP . The DS2775-DS2778 transition from sleep mode to active mode when DQ (SDA and SCL for 2-wire) changes logic state. See Figures 1 and 2 for more information on sleep-mode state. The DS2775-DS2778 have a "power switch" capability for waking the device and enabling the protection FETs when the host system is powered down. A simple dry contact switch on the PIO pin or DQ pin can be used to wake up the battery pack. The power-switch function is enabled using the PSPIO and PSDQ configuration bits in the Control register. When PSPIO or PSDQ are set and sleep mode is entered through the PMOD condition*, the PIO and DQ pins pull high, respectively. Sleep mode is exited upon the detection of a low-going transition on PIO or DQ. PIO has a 100ms debounce period to filter out glitches that can be caused when a sleeping battery is inserted into a system.
Power Modes
The DS2775-DS2778 have two power modes: active and sleep. On initial power-up, the DS2775-DS2778 default to active mode. In active mode, the DS2775- DS2778 are fully functional with measurements and capacity estimation registers continuously updated. The protector circuit monitors battery pack, cell voltages, and battery current for safe conditions. The protection FET gate drivers are enabled when conditions are deemed safe. Also, the SHA-1 authentication function is available in active mode. When an SHA-1 computation is performed, the supply current increases to IDD2 for tSHA. In sleep mode, the DS2775-DS2778 con-
*The "power switch" feature is disabled if sleep mode is entered because of a UV condition. 10 ______________________________________________________________________________________
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
ACTIVE PMOD = 0 UVEN = 0 RISING EDGE ON SDA OR SCL CHARGER DETECT SLEEP PSPIO = 0 PSDQ = X
ACTIVE PMOD = 0 UVEN = 0
RISING EDGE ON DQ CHARGER DETECT
SLEEP PSPIO = 0 PSDQ = 0
VIN1 OR VIN2 < VUV PULL DQ LOW ACTIVE PMOD = 0 UVEN = 1 VIN1 OR VIN2 < VUV CHARGER DETECT PULL PIO LOW PULL PIO LOW ACTIVE PMOD = 1 UVEN = 0 PULL DQ LOW FOR tSLEEP RISING EDGE ON DQ CHARGER DETECT PULL SDA AND SCL LOW FOR tSLEEP SLEEP PSPIO = 1 PSDQ = 0 ACTIVE PMOD = 1 UVEN = 0 RISING EDGE ON SDA OR SCL CHARGER DETECT SLEEP PSPIO = 1 PSDQ = X SLEEP PSPIO = 0 PSDQ = 1 ACTIVE PMOD = 0 UVEN = 1 RISING EDGE ON SDA OR SCL CHARGER DETECT SLEEP PSPIO = 0 PSDQ = X
PULL PIO LOW PULL DQ LOW FOR tSLEEP ACTIVE PMOD = 1 UVEN = 1 VIN1 OR VIN2 < VUV PULL DQ LOW CHARGER DETECT SLEEP PSPIO = 1 PSDQ = 1 ACTIVE PMOD = 1 UVEN = 1
VIN1 OR VIN2 < VUV PULL PIO LOW RISING EDGE ON SDA OR SCL CHARGER DETECT PULL SDA AND SCL LOW FOR tSLEEP SLEEP PSPIO = 1 PSDQ = X
Figure 1. Sleep-Mode State Diagram for DS2775/DS2776
Figure 2. Sleep-Mode State Diagram for DS2777/DS2778
Li+ Protection Circuitry
During active mode, the DS2775-DS2778 constantly monitor SNS, VIN1, VIN2, and PLS to protect the battery from overvoltage (overcharge), undervoltage (overdischarge), and excessive charge and discharge currents (overcurrent, short circuit). Table 1 summarizes the conditions that activate the protection circuit, the response of the DS2775-DS2778, and the thresholds that release the DS2775-DS2778 from a protection state. Figure 3 shows Li+ protection circuitry example waveforms.
Overvoltage (OV)
If either of the voltages on (VIN2 - VIN1) or (VIN1 - VSS) exceeds the overvoltage threshold, VOV, for a period longer than overvoltage delay, tOVD, the CC pin is driven low to shut off the external charge FET and the OV flag in the Protection register is set. The DC output remains high during overvoltage to allow discharging. When (V IN2 - V IN1) and (V IN1 - V SS) falls below the charge-enable threshold, VCE, the DS2775-DS2778 turn the charge FET on by driving CC high. The DS2775-DS2778 drive CC high before [(VIN2 - VIN1) and (VIN1 - VSS)] < VCE if a discharge condition persists with VSNS 1.2mV and [(VIN2 - VIN1) and (VIN1 VSS)] < VOV.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Table 1. Li+ Protection Conditions and DS2775/DS2776 Responses
CONDITION ACTIVATION THRESHOLD VCELL > VOV DELAY tOVD RESPONSE CC Off RELEASE THRESHOLD Both VCELL < VCE or (VSNS 1.2mV and both VCELL < VOV) (Note 1) VPLS > VIN2 (charger connected) or (both VCELL > VUV and UVEN = 0) (Note 3) VPLS < VDD - VTP (charger removed) (Note 4) VPLS > VDD - VTP (load removed) (Note 5) VPLS > VDD - VTP (Note 5)
Overvoltage (OV) (Note 1)
Undervoltage (UV) (Note 1)
VCELL < VUV
tUVD
CC Off, DC Off, Sleep Mode (Note 2) CC Off, DC Off DC Off DC Off
Overcurrent, Charge (COC) Overcurrent, Discharge (DOC) Short Circuit (SC)
VSNS < VCOC VSNS > VDOC VSNS > VSC
tOCD tOCD tSCD
Note 1: VCELL is defined as (VIN1 - VSS) or (VIN2 - VIN1). Note 2: Sleep mode is only entered if UVEN = 1. Note 3: If VCELL < VUV when a charger connection is detected, release is delayed until VCELL VUV. The recovery charge path provides an internal current limit (IRC) to safely charge the battery. Note 4: With test current IPPD flowing from PLS to VSS (pulldown on PLS) enabled. Note 5: With test current ITST flowing from VDD to PLS (pullup on PLS).
VIN
VOV VCE VUV
DISCHARGE VSC VSNS VDOC 0 -VCOC VOHCC VCP CC tOVD tOVD tOCD tUVD VDD VCP DC tSCO tOCD tUVD VPLS ACTIVE SLEEP*
CHARGE
POWER MODE
*IF UVEN = 1.
Figure 3. Li+ Protection Circuitry Example Waveforms
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Undervoltage (UV)
If the average of the voltages on (V IN2 - V IN1 ) or (VIN1 - VSS) drops below the undervoltage threshold, VUV, for a period longer than undervoltage delay, tUVD, the DS2775-DS2778 shut off the charge and discharge FETs and set the UV flag in the Protection register. If UVEN is set, the DS2775-DS2778 also enter sleep mode. When a charger is detected and VPLS > VIN2, the DS2775-DS2778 provide a current-limited recovery charge path (IRC) from PLS to VDD to gently charge severely depleted cells. The recovery charge path is enabled when 0 [(VIN2 - VIN1) and (VIN1 - VSS)] < V CE . The FETs remain off until (V IN2 - V IN1 ) and (VIN1 - VSS) exceed VUV. until the voltage on PLS rises above (VDD - VTP). The DS2775-DS2778 provide a test current of value ITST from VDD to PLS, pulling PLS up, in order to detect the removal of the offending low-impedance load.
DS2775/DS2776/DS2777/DS2778
Short Circuit (SC)
If V SNS exceeds short-circuit threshold, V SC , for a period longer than short-circuit delay, t SCD , the DS2775-DS2778 shut off the external discharge FET and set the DOC flag in the Protection register. The discharge current path is not reestablished until the voltage on PLS rises above (VDD - VTP). The DS2775- DS2778 provide a test current of value ITST from VDD to PLS, pulling PLS up, in order to detect the removal of the short circuit. All the protection conditions described are logic ANDed to affect the CC and DC outputs. CC = (overvoltage) AND (undervoltage) AND (overcurrent, charge direction) AND (Protection register bit CE = 0) DC = (undervoltage) AND (overcurrent, either direction) AND (short circuit) AND (Protection register bit DE = 0)
Overcurrent, Charge Direction (COC)
Charge current develops a negative voltage on VSNS with respect to VSS. If VSNS is less than the charge overcurrent threshold, VCOC, for a period longer than overcurrent delay, tOCD, the DS2775-DS2778 shut off both external FETs and set the COC flag in the Protection register. The charge current path is not reestablished until the voltage on the PLS pin drops below (VDD - VTP). The DS2775-DS2778 provide a test current of value I PPD from PLS to V SS , pulling PLS down, in order to detect the removal of the offending charge current source.
Voltage Measurements
Cell voltages are measured every 440ms. The lowest potential cell, VIN1, is measured with respect to VSS. The highest potential cell, V IN2 , is measured with respect to VIN1. Battery voltages are measured with a range of -5V to +4.9951V and a resolution of 4.8828mV and placed in the Result register in two's complement form. Voltages above the maximum register value are reported as 7FE0h.
Overcurrent, Discharge Direction (DOC)
Discharge current develops a positive voltage on VSNS with respect to VSS. If VSNS exceeds the discharge overcurrent threshold, VDOC, for a period longer than tOCD, the DS2775-DS2778 shut off the external discharge FET and set the DOC flag in the Protection register. The discharge current path is not reestablished
MSB - ADDRESS 0Ch, VIN1 - VSS MSB - ADDRESS 1Ch, VIN2 - VIN1 S MSb 29 28 27 26 25 24 23 LSb 22 MSb 21
LSB - ADDRESS 0Dh, VIN1 - VSS LSB - ADDRESS 1Dh, VIN2 - VIN1 20 X X X X X LSb
"S": SIGN BITS(S), "X": RESERVED
UNITS: 4.883mV
Figure 4. Voltage Register Format
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Temperature Measurement
The DS2775-DS2778 use an integrated temperature sensor to measure battery temperature with a resolution of 0.125C. Temperature measurements are updated every 440ms and placed in the Temperature register in two's complement form. 1.5625V. The input linearly converts peak signal amplitudes up to 102.4mV as long as the continuous signal level (average over the conversion cycle period) does not exceed 51.2mV. The ADC samples the input differentially at 18.6kHz and updates the Current register at the completion of each conversion cycle (3.52s). Charge currents above the maximum register value are reported as 7FFFh. Discharge currents below the minimum register value are reported as 8000h. The Average Current register reports an average current level over the preceding 28.16s. The register value is updated every 28.16s in two's complement form and represents an average of the eight preceding Current register values.
Current Measurement
In active mode, the DS2775-DS2778 continuously measure the current flow into and out of the battery by measuring the voltage drop across a low-value current-sense resistor, RSNS. The voltage-sense range between SNS and VSS is 51.2mV with a least significant bit (LSb) of
MSB--ADDRESS 0Ah S MSb "S": SIGN BIT(S), "X": RESERVED 29 28 27 26 25 24 23 LSb 22 MSb UNITS: 0.125C 21
LSB--ADDRESS 0Bh 20 X X X X X LSb
Figure 5. Temperature Register Format
MSB--ADDRESS 0Eh S MSb "S": SIGN BIT(S) 214 213 212 211 210 29 28 LSb 27 MSb 26
LSB--ADDRESS 0Fh 25 24 23 22 21 20 LSb
UNITS: 1.5625V/RSNS
Figure 6. Current Register Format
MSB--ADDRESS 08h S MSb "S": SIGN BIT(S) 214 213 212 211 210 29 28 LSb 27 MSb 26
LSB--ADDRESS 09h 25 24 23 22 21 20 LSb
UNITS: 1.5625V/RSNS
Figure 7. Average Current Register Format
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Current Offset Correction
Every 1024th conversion, the ADC measures its input offset to facilitate offset correction. Offset correction occurs approximately once per hour. The resulting correction factor is applied to the subsequent 1023 measurements. During the offset correction conversion, the ADC does not measure the sense resistor signal. A maximum error of 1/1024 in the Accumulated Current register (ACR) is possible; however, to reduce the error, the current measurement made just prior to the offset conversion is retained in the Current register and is substituted for the dropped current measurement in the current accumulation process. Therefore the accumulated current error due to offset correction is typically much less than 1/1024.
Current Blanking
The current blanking feature modifies current measurement result prior to being accumulated in the ACR. Current blanking occurs conditionally when a current measurement (raw current and COBR) falls in one of two defined ranges. The first range prevents charge currents less than 100V from being accumulated. The second range prevents discharge currents less than 25V in magnitude from being accumulated. Charge current blanking is always performed; however, discharge current blanking must be enabled by setting the NBEN bit in the Control register. See the Control Register Format description for additional information.
DS2775/DS2776/DS2777/DS2778
Current Measurement Gain
The DS2775-DS2778's current measurement gain can be adjusted through the RSGAIN register, which is factory calibrated to meet the data sheet specified accuracy. RSGAIN is user accessible and can be reprogrammed after module or pack manufacture to improve the current measurement accuracy. Adjusting RSGAIN can correct for variation in an external sense resistor's nominal value and allows the use of low-cost, nonprecision currentsense resistors. RSGAIN is an 11-bit value stored in 2 bytes of the parameter EEPROM memory block. The RSGAIN value adjusts the gain from 0 to 1.999 in steps of 0.001 (precisely 2-10). The user must use caution when programming RSGAIN to ensure accurate current measurement. When shipped from the factory, the gain calibration value is stored in two separate locations in the parameter EEPROM block, RSGAIN, which is reprogrammable and FRSGAIN, which is read-only. RSGAIN determines the gain used in the current measurement. The
Current Offset Bias
The current offset bias value (COB) allows a programmable offset value to be added to raw current measurements. The result of the raw current measurement plus COB is displayed as the current measurement result in the Current register and is used for current accumulation. COB can be used to correct for a static offset error or can be used to intentionally skew the current results and therefore the current accumulation. Read and write access is allowed to COB. Whenever the COB is written, the new value is applied to all subsequent current measurements. COB can be programmed in 1.56V steps to any value between -199.7V and +198.1V. The COBR value is stored as a two's complement value in volatile memory and must be initialized through the interface on power-up. The factory default value is 00h.
ADDRESS 7Bh S MSb "S": SIGN BIT(S) 26 25 24 23 22 21 20 LSb UNITS: 1.56V/RSNS
Figure 8. Current Offset Bias Register Format
MSB--ADDRESS 78h X MSb "S": SIGN BIT(S) SC0 OC1 OC0 X 20 2-1 2-2 LSb 2-3 MSb UNITS: 2-10 2-4
LSB--ADDRESS 79h 2-5 2-6 2-7 2-8 2-9 2-10 LSb
Figure 9. RSGAIN Register
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
FRSGAIN value is provided to preserve the factory calibration value only and is not used to calibrate the current measurement. The 16-bit FRSGAIN value is readable from addresses B0h and B1h. with the results displayed in the Accumulated Current register (ACR). The accuracy of the ACR is dependent on both the current measurement and the conversion time base. The ACR has a range of 0 to +409.6mVh with an LSb of 6.25Vh. Additional registers hold fractional results of each accumulation to avoid truncation errors. The fractional result bits are not user accessible. Accumulation of charge current above the maximum register value is reported at the maximum value; conversely, accumulation of discharge current below the minimum register value is reported at the minimum value. Charge currents (positive Current register values) less than 100V are not accumulated in order to mask the effect of accumulating small positive offset errors over long periods. This effect limits the minimum charge current, for coulomb counting purposes, to 5mA for RSNS = 0.020 and 20mA for RSNS = 0.005 (see Table 2 for more details). Read and write access is allowed to the ACR. The ACR must be written most significant byte (MSB) first, then LSB. Whenever the ACR is written, the fractional accumulation result bits are cleared. The write must be completed in 3.5s. A write to the ACR forces the ADC to perform an offset correction conversion and update the internal offset correction factor. The current measurement and accumulation begin with the second conversion following a write to the ACR. To preserve the ACR value in case of power loss, the ACR value is backed up to EEPROM. The ACR value is recovered from EEPROM on power-up. See the Memory Map for specific address location and backup frequency.
Sense-Resistor Temperature Compensation
The DS2775-DS2778 can temperature compensate the current-sense resistor to correct for variation in a sense resistor's value over temperature. The DS2775-DS2778 are factory programmed with the sense-resistor temperature coefficient, RSTC, set to zero, which turns off the temperature compensation function. RSTC is user accessible and can be reprogrammed after module or pack manufacture to improve the current accuracy when using a high-temperature coefficient currentsense resistor. RSTC is an 8-bit value stored in the parameter EEPROM memory block. The RSTC value sets the temperature coefficient from 0 to +7782ppm/C in steps of 30.5ppm/C. The user must program RSTC cautiously to ensure accurate current measurement. Temperature compensation adjustments are made when the Temperature register crosses 0.5C boundaries. The temperature compensation is most effective with the resistor placed as close as possible to the VSS terminal to optimize thermal coupling of the resistor to the on-chip temperature sensor. If the current shunt is constructed with a copper PCB trace, run the trace under the DS2775-DS2778 package whenever possible.
Current Accumulation
Current measurements are internally summed, or accumulated, at the completion of each conversion period
MSB--ADDRESS 10h 215 MSb "S": SIGN BIT(S) 214 213 212 211 210 29 28 LSb 27 MSb 26
LSB--ADDRESS 11h 25 24 23 22 21 20 LSb
UNITS: 6.25V/RSNS
Figure 10. Accumulated Current Register Format
Table 2. Resolution and Range vs. Sense Resistor
TYPE OF RESOLUTION/RANGE Current Resolution Current Range ACR Resolution ACR Range VSS - VSNS 1.5625V 51.2mV 6.25Vh 409.6mVh RSNS 20m 78.13A 2.56A 312.5Ah 20.48Ah 15m 104.2A 3.41A 416.7Ah 27.30Ah 10m 156.3A 5.12A 625Ah 40.96Ah 5m 312.5A 10.2A 1.250mAh 81.92Ah
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Accumulation Bias
In some designs a systematic error or an application preference requires the application of an arbitrary bias to the current accumulation process. The Current Accumulation Bias register (CAB) allows a user-programmed constant positive or negative polarity bias to be included in the current accumulation process. The value in CAB can be used to estimate battery currents that do not flow through the sense resistor, estimate battery self-discharge, or estimate current levels below the current measurement resolution. The user-programmed two's complement value, with bit weighting the same as the current register, is added to the ACR once per current conversion cycle. CAB is loaded on power-up from EEPROM memory.
Modeling Cell Characteristics
To achieve reasonable accuracy in estimating remaining capacity, the cell performance characteristics over temperature, load current, and charge-termination point must be considered. Since the behavior of Li+ cells is nonlinear, these characteristics must be included in the capacity estimation to achieve an acceptable level of accuracy in the capacity estimation. The FuelPack method used in the DS2775-DS2778 is described in general in Application Note 131: Lithium-Ion Cell Fuel Gauging with Maxim Battery Monitor ICs. To facilitate efficient implementation in hardware, a modified version of the method outlined in Application Note 131 is used to store cell characteristics in the DS2775-DS2778. Full and empty points are retrieved in a lookup process that retraces a piecewise linear model consisting of three model curves named full, active empty, and standby empty. Each model curve is constructed with five line segments, numbered 1 through 5. Above +40C, the segment 5 model curves extend infinitely with zero slope, approximating the nearly flat change in capacity of Li+ cells at temperatures above +40C. Segment 4 of each model curves originates at +40C on its upper end and extends downward in temperature to the junction with segment 3. Segment 3 joins with segment 2, which in turn joins with segment 1. Segment 1 of each model curve extends from the junction with segment 2 to infinitely colder temperatures. The three junctions or breakpoints that join the segments (labeled TBP12, TBP23, and TBP34 in Figure 14) are programmable in 1C increments from -128C to +40C. The slope or derivative for segments 1, 2, 3, and 4 are also programmable over a range of 0 to 15,555ppm in steps of 61ppm.
DS2775/DS2776/DS2777/DS2778
Cycle Counter
The cycle counter is an absolute count of the cumulative discharge cycles. This register is intended to act as a "cell odometer." The LSb is two cycles, which allows a maximum count of 510 discharge cycles. The register does not loop. Once the maximum value is reached, the register is clamped. This register is read and write accessible while the parameter EEPROM memory block (block 1) is unlocked. The Cycle Count register becomes read-only once the EEPROM block is locked.
Capacity Estimation Algorithm
Remaining capacity estimation uses real-time measured values and stored parameters describing the cell characteristics and application operating limits. Figure 13 describes the algorithm inputs and outputs.
ADDRESS 61h S MSb "S": SIGN BIT(S) 26 25 24 23 22 21 20 LSb UNITS: 6.25V/RSNS
Figure 11. Current Accumulation Bias Register Format
ADDRESS 1Eh 27 MSb 26 25 24 23 22 21 20 LSb UNITS: 2 cycles
Figure 12. Cycle Counter Register Format
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
VOLTAGE TEMPERATURE CURRENT ACCUMULATED CURRENT (ACR) (RW) (R) (R) CAPACITY LOOKUP (R) AVAILABLE CAPACITY CALCULATION ACR HOUSEKEEPING AGE ESTIMATOR AVERAGE CURRENT (R) LEARN FUNCTION STANDBY EMPTY SE(T) (R) FULL ACTIVE EMPTY FULL(T) AE(T) (R) (R)
REMAINING ACTIVE-ABSOLUTE CAPACITY (RAAC) mAh (R) REMAINING STANDBY-ABSOLUTE CAPACITY (RSAC) mAh (R) REMAINING ACTIVE-RELATIVE CAPACITY (RARC) % (R)
CELL MODEL PARAMETERS (EEPROM)
REMAINING STANDBY-RELATIVE CAPACITY (RSRC) % (R)
AGING CAPACITY (AC) (2 BYTES EE) AGE SCALAR (AS) (1-BYTE EE) SENSE-RESISTOR PRIME (RSNSP) (1-BYTE EE) CHARGE VOLTAGE (VCHG) (1-BYTE EE) MINIMUM CHARGE CURRENT (IMIN) (1-BYTE EE) ACTIVE-EMPTY VOLTAGE (VAE) (1-BYTE EE) ACTIVE-EMPTY CURRENT (IAE) (1-BYTE EE)
USER MEMORY (EEPROM) 16 BYTES
CYCLE COUNTER (EEPROM)
Figure 13. Top-Level Algorithm Diagram
Full
The full curve defines how the full point of a given cell depends on temperature for a given charge termination. The application's charge termination method should be used to determine the table values. The DS2775-DS2778 reconstruct the full line from cell characteristic table values to determine the full capacity of the battery at each temperature. Reconstruction occurs in one-degree temperature increments.
Active Empty
The active-empty curve defines the variation of the active-empty point over temperature. The active-empty point is defined as the minimum voltage required for system operation at a discharge rate based on a highlevel load current (one that is sustained during a highpower operating mode). This load current is programmed as the active-empty current (IAE), and should be a 3.5s average value to correspond to values
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
SEGMENT 1 100%
SEGMENT 2
SEGMENT 3
SEGMENT 4
SEGMENT 5
DERIVATIVE (ppm/C)
FULL
CELL CHARACTERIZATION DATA CHARACTERIZATION ACTIVE EMPTY
STANDBY EMPTY
TBP12
TBP23
TBP34
+40C
Figure 14. Cell Model Example Diagram
read from the Current register. The specified minimum voltage, or active-empty voltage (VAE), should be a 110ms average value to correspond to the values read from the voltage register. The VAE value represents the average of the two cell's voltages, VIN1 and VIN2. The DS2775-DS2778 reconstruct the active-empty line from the cell characteristic table to determine the activeempty capacity of the battery at each temperature. Reconstruction occurs in one-degree temperature increments.
Standby Empty
The standby-empty curve defines the variation of the standby-empty point over temperature. The standbyempty point is defined as the minimum voltage required for standby operation at a discharge rate dictated by the application standby current. In typical handheld applications, standby empty represents the point that the battery can no longer support DRAM refresh and
thus the standby voltage is set by the minimum DRAM voltage-supply requirements. In other applications, standby empty can represent the point that the battery can no longer support a subset of the full application operation, such as games or organizer functions. The standby-load current and voltage are used for determining the cell characteristics but are not programmed into the DS2775-DS2778. The DS2775-DS2778 reconstruct the standby-empty line from the cell characteristic table to determine the standby-empty capacity of the battery at each temperature. Reconstruction occurs in one-degree temperature increments.
Cell Model Construction
The model is constructed with all points normalized to the fully charged state at +40C. All values are stored in the cell parameter EEPROM block. The +40C full value is stored in Vh with an LSb of 6.25Vh. The +40C active-empty value is stored as a percentage of +40C
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
full with a resolution of 2-10. Standby empty at +40C is, by definition, zero and therefore no storage is required. The slopes (derivatives) of the four segments for each model curve are stored in the cell parameter EEPROM block as ppm/C. The breakpoint temperatures of each segment are stored there also (refer to Application Note 3584: Storing Battery Fuel Gauge Parameters in DS2780 for more details on how values are stored). An example of data stored in this manner is shown in Table 3.
Application Parameters
In addition to cell model characteristics, several application parameters are needed to detect the full and empty points, as well as calculate results in mAh units.
Sense Resistor Prime (RSNSP)
RSNSP stores the value of the sense resistor for use in computing the absolute capacity results. The value is stored as a 1-byte conductance value with units of mhos (1/). RSNSP supports resistor values of 1 to 3.922m. RSNSP is located in the parameter EEPROM block. RSNSP = 1/RSNS (units of mhos; 1/)
CELL MODEL PARAMETERS (EEPROM) TEMPERATURE LOOKUP FUNCTION
FULL(T) AE(T) SE(T)
Charge Voltage (VCHG)
VCHG stores the charge voltage threshold used to detect a fully charged state. The voltage is stored as a 1-byte value with units of 19.5mV and can range from 0 to 4.978V. VCHG should be set marginally less than the average cell voltage at the end of the charge cycle to ensure reliable charge termination detection. VCHG is located in the parameter EEPROM block.
Figure 15. Lookup Function Diagram
Table 3. Example Cell Characterization Table (Normalized to +40C)
Manufacturer's Rated Cell Capacity: 1000mAh Charge Voltage: 4.2V Active Empty (V): 3.0V Sense Resistor: 0.020 SEGMENT BREAKPOINTS TBP12 = -12C TBP23 = 0C TBP34 = 18C Termination Current: 50mA Standby Empty (I): 300mA
CALCULATED VALUE Full Active Empty Standby Empty
+40C NOMINAL (mAh) 1051
SEGMENT 1 (ppm/C) 3601 2380 1404
SEGMENT 2 (ppm/C) 3113 1099 427
SEGMENT 3 (ppm/C) 1163 671 244
SEGMENT 4 (ppm/C) 854 305 183
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Minimum Charge Current (IMIN)
IMIN stores the charge-current threshold used to detect a fully charged state. It is stored as a 1-byte value with units of 50V (IMIN x RSNS) and can range from 0 to 12.75mV. Assuming RSNS = 20m, IMIN can be programmed from 0 to 637.5mA in 2.5mA steps. IMIN should be set marginally greater than the charge current at the end of the charge cycle to ensure reliable charge termination detection. IMIN is located in the parameter EEPROM block. time of pack manufacture to allow the learning of a larger capacity on batteries that have an initial capacity greater than the rated cell capacity programmed in the cell characteristic table. The AS is modified by aging estimation introduced under aging capacity and by the learn function. Batteries are typically considered worn out when the full capacity reaches 80% of the rated capacity; therefore, the AS value is not required to range to 0%. It is clamped to 50% (64 decimal or 40h). If a value of 50% is read from the AS, the host should prompt the user to initiate a learning cycle. The host system has read and write access to the AS; however, caution should be exercised when writing it to ensure that the cumulative aging estimate is not overwritten with an incorrect value. The AS is automatically saved to EEPROM. The EEPROM value is recalled on power-up.
DS2775/DS2776/DS2777/DS2778
Active-Empty Voltage (VAE)
VAE stores the voltage threshold used to detect the active-empty point. The value is stored in 1 byte with units of 19.5mV and can range from 0 to 4.978V. VAE is stored as an average of the cell's voltages. VAE is located in the parameter EEPROM block. See the Modeling Cell Characteristics section for more information.
Active-Empty Current (IAE)
IAE stores the discharge-current threshold used to detect the active-empty point. The unsigned value represents the magnitude of the discharge current and is stored in 1 byte with units of 200V and can range from 0 to 51.2mV. Assuming RSNS = 20m, IAE can be programmed from 0 to 2550mA in 10mA steps. IAE is located in the parameter EEPROM block. See the Modeling Cell Characteristics section for more information.
Capacity Estimation Operation
Cycle-Count-Based Aging Estimation
As previously discussed, the AS register value is adjusted occasionally based on cumulative discharge. As the ACR register decrements during each discharge cycle, an internal counter is incremented until equal to 32 times the AC. The AS is then decremented by one, resulting in a decrease of the scaled full battery capacity by 0.78% (approximately 2.4% per 100 cycles). The internal counter is reset in the event of a learn cycle. See the Aging Capacity (AC) section for recommendations on customizing the age estimation rate.
Aging Capacity (AC)
AC stores the rated cell capacity, which is used to estimate the decrease in battery capacity that occurs during normal use. The value is stored in 2 bytes in the same units as the ACR (6.25Vh). When set to the manufacturer's rated cell capacity, the aging estimation rate is approximately 2.4% per 100 cycles of equivalent full capacity discharges. Partial discharge cycles are added to form equivalent full capacity discharges. The default aging estimation results in 88% capacity after 500 equivalent cycles. The aging estimation rate can be adjusted by setting the AC to a value other than the cell manufacturer's rating. Setting AC to a lower value accelerates the aging estimation rate. Setting AC to a higher value retards the aging estimation rate. The AC is located in the parameter EEPROM block.
Learn Function
Because Li+ cells exhibit charge efficiencies near unity, the charge delivered to a Li+ cell from a known empty point to a known full point is a dependable measure of the cell's capacity. A continuous charge from empty to full results in a learn cycle. First, the active-empty point must be detected. The learn flag (LEARNF) is set at this point. Then, once charging starts, the charge must continue uninterrupted until the battery is charged to full. Upon detecting full, the LEARNF is cleared, the chargeto-full (CHGTF) flag is set, and the AS is adjusted according to the learned capacity of the cell. Full capacity estimation based on the learn function is more accurate than the cycle-count-based estimation introduced under aging capacity. The learn function reflects the current performance of the cell. Cyclecount-based estimation is an approximation derived from the manufacturer's recommendation for a typical cell. Therefore, the internal counter used for cycle-
Age Scalar (AS)
AS adjusts the cell capacity estimation results downward to compensate for aging. The AS is a 1-byte value that has a range of 49.2% to 100%. The LSb is weighted at 0.78% (precisely 2-7). A value of 100% (128 decimal or 80h) represents an unaged battery. A value of 95% is recommended as the starting AS value at the
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
count-based estimation is reset after a learn cycle. The cycle-count-based estimation is used only in the absence of a learn cycle. level with the discharge rate ensures that the activeempty point is not detected at loads much lighter than those used to construct the model. Also, the activeempty point must not be detected when a deep discharge at a very light load is followed by a load greater than IAE. Either case would cause a learn cycle on the following charge to include part of the standby capacity in the measurement of the active capacity. Activeempty point detection sets the learn flag (LEARNF) bit in the Status register. Note: Do not confuse the active-empty point with the active-empty flag. The active-empty flag is set only when the VAE threshold is passed.
ACR Housekeeping
The ACR value is adjusted occasionally to maintain the coulomb count within the model curve boundaries. When the battery is charged to full (CHGTF set), the ACR is set equal to the age-scaled full lookup value at the present temperature. If a learn cycle is in progress, correction of the ACR value occurs after the AS is updated. When an empty condition is detected (LEARNF and/or AEF set), the ACR adjustment is conditional: * If the AEF is set and the LEARNF is not set, the active-empty point was not detected. The battery is likely below the active-empty capacity of the model. The ACR is set to the active-empty model value at present temperature only if it is greater than the active-empty model value at present temperature. * If the AEF is set, the LEARNF is not set, and the ACR is below the active-empty model value at present temperature, the ACR is not updated. * If the LEARNF is set, the battery is at the activeempty point and the ACR is set to the active-empty model value.
Result Registers
The DS2775-DS2778 process measurement and cell characteristics on a 3.5s interval and yield seven result registers. The result registers are sufficient for direct display to the user in most applications. The host system can produce customized values for system use or user display by combining measurement, result, and user EEPROM values.
FULL(T)
The full capacity of the battery at the present temperature is reported normalized to the +40C full value. This 15-bit value reflects the cell model full value at the given temperature. The FULL(T) register reports values between 100% and 50% with a resolution of 61ppm (precisely 2-14). Though the register format permits values greater than 100%, the register value is clamped to a maximum value of 100%.
Full Detect
Full detection occurs when the average of VIN1 and VIN2 voltage registers remain continuously above the charge voltage (VCHG) threshold for the duration of two average current (IAVG) readings, and both IAVG readings are below terminating current (IMIN). The two consecutive IAVG readings must also be positive and nonzero (>16 LSB). This ensures that removing the battery from the charger does not result in a false detection of full. Full detect sets the charge to full (CHGTF) bit in the Status register.
Active Empty, AE(T)
The active-empty capacity of the battery at the present temperature is reported normalized to the +40C full value. This 13-bit value reflects the cell model activeempty value at the given temperature. The AE(T) register reports values between 0% and 49.8% with a resolution of 61ppm (precisely 2-14).
Active-Empty Point Detect
Active-empty point detection occurs when the average of VIN1 and VIN2 voltage registers drops below the VAE threshold and the two previous current readings are above IAE. This captures the event of the battery reaching the active-empty point. Note that the two previous current readings must be negative and greater in magnitude than IAE (i.e., a larger discharge current than specified by the IAE threshold). Qualifying the voltage
Standby Empty, SE(T)
The standby-empty capacity of the battery at the present temperature is reported normalized to the +40C full value. This 13-bit value reflects the cell model standby-empty value at the current temperature. The SE(T) register reports values between 0% and 49.8% with a resolution of 61ppm (precisely 2-14).
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
MSB--ADDRESS 02h 215 MSb 214 213 212 211 210 29 28 LSb 27 MSb UNITS: 1.6mAh 26 LSB--ADDRESS 03h 25 24 23 22 21 20 LSb
Figure 16. Remaining Active Absolute Capacity (RAAC) [mAh]
The RAAC register reports the capacity available under the current temperature conditions to the the active-empty point in absolute units of milliamps/hour (mAh). RAAC is 16 bits.
MSB--ADDRESS 04h 215 MSb 214 213 212 211 210 29 28 LSb 27 MSb UNITS: 1.6mAh 26 LSB--ADDRESS 05h 25 24 23 22 21 20 LSb
Figure 17. Remaining Standby Absolute Capacity (RSAC) [mAh]
The RSAC register reports the remaining battery capacity available under the current temperature conditions to the standby-empty point capacity in absolute units of milliamps/hour (mAh). RSAC is 16 bits.
MSB-ADDRESS 06h 215 MSb 214 213 212 211 210 29 28 LSb UNITS: 1%
Figure 18. Remaining Active Relative Capacity (RARC) [%]
The RARC register reports the remaining battery capacity available under the current temperature conditions to the active-empty point in relative units of percent (%). RARC is 8 bits.
MSB-ADDRESS 07h 215 MSb 214 213 212 211 210 29 28 LSb UNITS: 1%
Figure 19. Remaining Standby Relative Capacity (RSRC) [%]
The RSRC register reports the remaining battery capacity available under the current temperature conditions to the standby-empty point capacity in relative units of percent (%). RSRC is 8 bits.
Calculation of Results
RAAC [mAh] = (ACR[mVh] - AE(T) x FULL40[mVh]) x RSNSP [mhos]* RSAC [mAh] = (ACR[mVh] - SE(T) x FULL40[mVh]) x RSNSP [mhos]* RARC [%] = 100% x (ACR[mVh] - AE(T) x FULL40[mVh])/{(AS x FULL(T) - AE(T)) x FULL40[mVh]} RSRC [%] = 100% x (ACR[mVh] - SE(T) x FULL40[mVh])/{(AS x FULL(T) - SE(T)) x FULL40[mVh]}
*RSNSP = 1/RSNS
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Protection, Status, and Control Registers
Protection Register Format
The Protection register reports events detected by the Li+ safety circuit on bits [7:2]. Bits 0 and 1 are used to disable the charge and discharge FET gate drivers. Bits [7:2] are set by internal hardware only. Bits 2 and 3 are cleared by hardware only. Bits [7:4] are cleared by writing the register with a 0 in the bit position of interest. Writing a 1 to bits [7:4] has no effect on the register. Bits 0 and 1 are set on power-up and a transition from sleep to active modes. While in active mode, these bits can be cleared to disable the FET gate drive of either or both FETs. Setting these bits only turns on the FETs if there are no protection faults.
Protection Register (00h)
BIT 7 OV BIT 6 UV BIT 5 COC BIT 4 DOC BIT 3 CC BIT 2 DC BIT 1 CE BIT 0 DE
Bit 7: Overvoltage Flag (OV). OV is set to indicate that an overvoltage condition has been detected. The average of the voltages on VIN1 and VIN2 has persisted above the OV threshold for tOVD. OV remains set until written to 0, cleared by a power-on reset, or transitioned to sleep mode. Bit 6: Undervoltage Flage (UV). UV is a read-only mirror of the UVF flag located in the Status register. UVF is set to indicate that the average of the voltages on VIN1 and VIN2 has persisted below the UV threshold for tUVD. The UVF bit must be written to 0 to clear UV and UVF. Bit 5: Charge Overcurrent Flag (COC). COC is set to indicate that an overcurrent condition has occurred while charging. The sense-resistor voltage has persisted above the COC threshold for tOCD. COC remains set until written to 0, cleared by a power-on reset, or transitioned to sleep mode. Bit 4: Discharge Overcurrent Flag (DOC). DOC is set to indicate that an overcurrent condition has occurred while discharging. The sense-resistor voltage has persisted above the DOC threshold for tOCD. DOC remains set until written to 0, cleared by a power-on reset, or transitioned to sleep mode. Bit 3: Charge Control Flag (CC). CC indicates the logic state of the CC pin driver. The CC flag is set to indicate CC high and is cleared to indicate CC low. The CC flag is read-only. Bit 2: Discharge Control Flag (DC). DC indicates the logic state of the DC pin driver. DC flag is set to indicate DC high and is cleared to indicate DC low. DC flag is read-only. Bit 1: Charge-Enable Bit (CE). CE must be set to allow the CC pin to drive the charge FET to the on state. CE acts as an enable input to the safety circuit. If all safety conditions are met and CE is set, the CC pin drives to VCP. If CE is cleared, the CC pin is driven low to disable the charge FET. The power-up default state of CE is 1. Bit 0: Discharge-Enable Bit (DE). DE must be set to allow the DC pin to drive the discharge FET to the on state. DE acts as an enable input to the safety circuit. If all safety conditions are met and DE is set, the DC pin drives to VCP. If DE is cleared, the DC pin is driven low to disable the discharge FET. The power-up default state of DE is 1.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Status Register Format
The Status register contains bits that report the device status. All bits are set internally. The CHGTF, AEF, SEF, and LEARNF bits are read-only. The UVF and PORF bits can be cleared by writing a 0 to the bit locations.
DS2775/DS2776/DS2777/DS2778
Status Register (01h)
BIT 7 CHGTF BIT 6 AEF BIT 5 SEF BIT 4 LEARNF BIT 3 X BIT 2 UVF BIT 1 PORF BIT 0 X
Bit 7: Charge-Termination Flag (CHGTF). CHGTF is set to indicate that the average of the voltages on VIN1 and VIN2 and the Average Current register values have persisted above the VCHG and below the IMIN thresholds sufficiently long enough to detect a fully charged condition. CHGTF is cleared when RARC is less than 90%. CHGTF is read-only. Bit 6: Active-Empty Flag (AEF). AEF is set to indicate that the battery is at or below the active-empty point. AEF is set when the average of the voltages on VIN1 and VIN2 is less than the VAE threshold. AEF is cleared when RARC is greater than 5%. AEF is read-only. Bit 5: Standby-Empty Flag (SEF). SEF is set to indicate RSRC is less than 10%. SEF is cleared when RSRC is greater than 15%. SEF is read-only. Bit 4: Learn Flag (LEARNF). LEARNF indicates that the current-charge cycle can be used to learn the battery capacity. LEARNF is set when the active-empty point is detected. This occurs when the average of the voltages on VIN1 and VIN2 drops below the VAE threshold and the two previous current register values were negative and greater in magnitude than the IAE threshold. See the Active-Empty Point Detect section for additional information. LEARNF is cleared when any of the following occur: 1) Learn cycle completes (CHGTF set). 2) Current register value becomes negative indicating discharge current flow. 3) ACR = 0. 4) ACR value is written or recalled from EEPROM. 5) Sleep mode is entered. LEARNF is read-only. Bit 3 and 0: Reserved. Bit 2: Undervoltage Flag (UVF). UVF is set to indicate that the average of the voltages on VIN1 and VIN2 is less than VUV and must be written to 0 to allow subsequent undervoltage events to be reported. UVF is not cleared internally. Writing UVF to 0 is effective only when the average of the voltages on VIN1 and VIN2 is greater than or equal to VUV, otherwise, UVF remains set due to the persistent undervoltage condition. UVF is set on power-up. Bit 1: Power-On Reset Flag (PORF). PORF is set to indicate initial power-up. PORF is not cleared internally. The user must write this flag value to a 0 to use it to indicate subsequent power-up events. If PORF indicates a power-on reset, the ACR could be misaligned with the actual battery state of charge. The system can request a charge to full to synchronize the ACR with the battery charge state. PORF is read/write to 0.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Control Register Format
All Control register bits are read and write accessible. The Control register is recalled from parameter EEPROM memory at power-up. Register bit values can be modified in shadow RAM after power-up. Power-up default values are saved by using the Copy Data command.
Control Register (60h)
BIT 7 NBEN BIT 6 UVEN BIT 5 PMOD BIT 4 RNAOP BIT 3 VUV1 BIT 2 VUV0 BIT 1 PSPIO BIT 0 PSDQ
Bit 7: Negative Blanking Enable (NBEN). A value of 1 enables blanking of negative current values up to 25V. A value of 0 disables blanking of negative currents. The power-up default of NBEN = 0. Bit 6: Undervoltage Enable (UVEN). A value of 1 allows the DS2775-DS2778 to enter sleep mode when the average of the voltages on VIN1 and VIN2 is less than VUV and DQ is stable at either logic level for tSLEEP. A value of 0 disables transitions to sleep mode during an undervoltage condition. Bit 5: Power-Mode Enable (PMOD). A value of 1 allows the DS2775-DS2778 to enter sleep mode when DQ is low for tSLEEP. A value of 0 disables DQ-related transitions to sleep mode. Bit 4: Read Net Address Op Code (RNAOP). A value of 0 selects 33h as the op code value for the Read Net Address command. A value of 1 selects 39h as the op code value for the Read Net Address command. Bit 3 and 2: Undervoltage Threshold (VUV[1:0]). Sets the voltage at which the part detects an undervoltage condition according to Table 4. Bit 1: Power-Switch PIO Enable (PSPIO). A value of 1 enables the PIO pin as a power-switch input. A value of 0 disables the power-switch input function on PIO pin. This control is independent of the PSDQ state. Bit 0: Power-Switch DQ Enable (PSDQ). A value of 1 enables the DQ pin as a power-switch input. A value of 0 disables the power-switch input function on DQ pin. This control is independent of the PSPIO state. This bit has no effect in the DS2777/DS2778.
Table 4. Undervoltage Threshold
VUV[1:0] BIT FIELD 00 01 10 11 VUV (V) 2.00 2.30 2.45 2.60
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Overvoltage Threshold Register Format
The 8-bit Overvoltage Threshold register (VOV) sets the overvoltage threshold for the protection circuitry. An overvoltage condition is detected if either of the voltages on VIN1 or VIN2 exceeds the OV threshold for tOVD. The LSB of the VOV register is 2 x 5V/1024 = 31.25mV. The VOV set point can be calculated by the following formula. VOV = (678 + 2 x Overvoltage_Threshold_Register_Value) x 5V/1024 Example: Overvoltage Threshold register = 1110110b = 118D VOV = (678 + 2 x 118) x 5V/1024 = 4.46289V
DS2775/DS2776/DS2777/DS2778
Overvoltage Threshold Register (7Fh)
BIT 7 X BIT 6 VOV6 BIT 5 VOV5 BIT 4 VOV4 BIT 3 VOV3 BIT 2 VOV2 BIT 1 VOV1 BIT 0 VOV0
Table 5. VOV Register Programmability
VOV[6:0] BIT FIELD 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 ... V OV 3.311 3.320 3.330 3.340 3.350 3.359 3.369 3.379 3.389 3.398 3.408 3.418 3.428 3.438 3.447 3.457 ... VOV[6:0] BIT FIELD 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011 1111100 1111101 1111110 1111111 V OV 4.404 4.414 4.424 4.434 4.443 4.453 4.463 4.473 4.482 4.492 4.502 4.512 4.521 4.531 4.541 4.551
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Overcurrent Thresholds
The overcurrent thresholds are set in the upper nibble of the RSGAIN register. The OC1 and OC0 bits set the overcurrent thresholds for the charge and discharge thresholds. The short-circuit threshold is set by the SC0 bit (see Tables 6 and 7, respectively, for overcurrent and short-circuit threshold values). The DS2775-DS2778 have a built-in fixed delay of tOCD for overcurrent events and tSCD for short-circuit events. This means that the current ADC must read a value greater than the overcurrent threshold for longer than tOCD and greater than the short-circuit threshold for longer than tSCD before turning off the FET. Overcurrent and short-circuit events less than their respective delays are ignored.
ADDRESS 78h X MSb SC0 OC1 OC0 X 20 2-1 2-2 LSb
Figure 20. Overcurrent and Short-Circuit Threshold Bits Format
Table 6. COC, DOC Programmability
OC[1:0] BIT FIELD 00 01 10 11 VCOC (mV) -25 -38 -50 -75 VDOC (mV) 38 50 75 100
Table 7. SC Programmability
SC0 BIT FIELD 0 1 VSC (mV) 150 300
Special Feature Register Format
All register bits are read and write accessible with default values specified in each bit definition.
Special Feature Register (15h)
BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 SHA_IDLE BIT 0 PIOB
Bits 7 to 2: Reserved. Bit 1: SHA Idle Bit (SHA_IDLE). For the DS2777/DS2778, this bit reads logic 1 while an SHA calculation is in progress and reads logic 0 when the calculation is complete. Bit 0: PIO Pin Sense and Control Bit (PIOB). Writing a 0 to the PIOB bit activates the PIO pin open-drain output driver, forcing the PIO pin low. Writing a 1 to PIOB disables the output driver, allowing the PIO pin to be pulled high or used as an input. Reading PIOB returns the logic level forced on the PIO pin. Note that if the PIO pin is left unconnected with PIOB set, a weak pulldown current source pulls the PIO pin to VSS. PIOB is set to a 1 on power-up. PIOB is also set in sleep mode to ensure the PIO pin is high-impedance in sleep mode. Note: Do not write PIOB to 0 if PSPIO is enabled.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
EEPROM Register
The EEPROM register provides access control of the EEPROM blocks. EEPROM blocks can be locked to prevent alteration of data within the block. Locking a block disables write access to the block. Once a block is locked, it cannot be unlocked. Read access to EEPROM blocks is unaffected by the lock/unlock status.
DS2775/DS2776/DS2777/DS2778
EEPROM Register Format (1Fh)
BIT 7 EEC BIT 6 LOCK BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 BL1 BIT 0 BL0
Bit 7: EEPROM Copy Flag (EEC). A 1 in this read-only bit indicates that a Copy Data command is in progress. While this bit is high, writes to EEPROM addresses are ignored. A 0 value in this bit indicates that data can be written to unlocked EEPROM. Bit 6: EEPROM Lock Enable (LOCK). When the LOCK bit is 0, the Lock command is ignored. Writing a 1 to this bit enables the Lock command. After setting the LOCK bit, the Lock command must be issued as the next command, else the LOCK bit is reset to 0. After the lock operation is completed, the LOCK bit is reset to 0. The LOCK bit is a volatile R/W bit, initialized to 0 upon POR. Bits 5 to 2: Reserved. Bit 1: Parameter EEPROM Block 1 Lock Flag (BL1). A 1 in this read-only bit indicates that EEPROM block 1 (addresses 60h to 80h) is locked (read-only), while a 0 indicates block 1 is unlocked (read/write). Bit 0: User EEPROM Block 0 Lock Flag (BL0). A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20h to 2Fh) is locked (read-only), while a 0 indicates block 0 is unlocked (read/write).
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Memory
The DS2775-DS2778 have a 256-byte linear memory space with registers for instrumentation, status, and control, as well as EEPROM memory blocks to store parameters and user information. Byte addresses designated as "reserved" typically return FFh when read. These bytes should not be written. Several byte registers are paired into 2-byte registers to store 16-bit values. The MSB of the 16-bit value is located at the even address and the LSB is located at the next address (odd) byte. When the MSB of a 2-byte register is read, the MSB and LSB are latched simultaneously and held for the duration of the Read Data command to prevent updates to the LSB during the read. This ensures synchronization between the two register bytes. For consistent results, always read the MSB and the LSB of a 2-byte register during the same Read Data sequence. EEPROM memory consists of nonvolatile EEPROM cells overlaying volatile shadow RAM. The Read Data and Write Data commands allow the 1-Wire interface to directly accesse the shadow RAM (Figure 21). The Copy Data and Recall Data commands transfer data between the EEPROM cells and the shadow RAM. In order to modify the data stored in the EEPROM cells, data must be written to the shadow RAM and then copied to the EEPROM. To verify the data stored in the EEPROM cells, the EEPROM data must be recalled to the shadow RAM and then read from the shadow. After issuing the Copy Data command, access to the EEPROM block is not available until the EEPROM copy completes (see t EEC in the EEPROM Reliability Specification table).
User EEPROM--Block 0
A 16-byte user EEPROM memory (block 0, addresses 20h to 2Fh) provides nonvolatile memory that is uncommitted to other DS2775-DS2778 functions. Accessing the user EEPROM block does not affect the operation of the DS2775-DS2778. User EEPROM is lockable and, once locked, write access is not allowed. The battery pack or host system manufacturer can program lot codes, date codes, and other manufacturing or warranty or diagnostic information and then lock it to safeguard the data. User EEPROM can also store parameters for charging to support different size batteries in a host device as well as auxiliary model data such as time to full-charge estimation parameters.
Parameter EEPROM--Block 1
Model data for the cells as well as application operating parameters are stored in the parameter EEPROM memory (block 1, addresses 60h to 80h). The ACR (MSB and LSB) and AS registers are automatically saved to EEPROM when the RARC result crosses 4% boundaries (see Table 8 for more information).
COPY
EEPROM
WRITE SERIAL INTERFACE READ SHADOW RAM
RECALL
Figure 21. EEPROM Access Through Shadow RAM
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Table 8. Parameter EEPROM Memory Block
ADDRESS (HEX) 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h Control Register Accumulation Bias Register (AB) Aging Capacity Register MSB (AC) Aging Capacity Register LSB (AC) Charge Voltage Register (VCHG) Minimum Charge Current Register (IMIN) Active-Empty Voltage Register (VAE) Active-Empty Current Register (IAE) Active-Empty 40 Register Sense Resistor Prime Register (RSNSP) Full 40 MSB Register Full 40 LSB Register Full Segment 4 Slope Register Full Segment 3 Slope Register Full Segment 2 Slope Register Full Segment 1 Slope Register AE Segment 4 Slope Register DESCRIPTION ADDRESS (HEX) 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch 7Dh 7Eh 7Fh 80h DESCRIPTION AE Segment 3 Slope Register AE Segment 2 Slope Register AE Segment 1 Slope Register SE Segment 4 Slope Register SE Segment 3 Slope Register SE Segment 2 Slope Register SE Segment 1 Slope Register Sense-Resistor Gain Register MSB (RSGAIN) Sense-Resistor Gain Register LSB (RSGAIN) Sense-Resistor Temperature Coefficient Register (RSTC) Current Offset Bias Register (COB) TBP34 Register TBP23 Register TBP12 Register Protector Threshold Register 2-Wire Slave Address Register
DS2775/DS2776/DS2777/DS2778
Table 9. Memory Map
ADDRESS (HEX) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h Protection Register Status Register RAAC Register MSB RAAC Register LSB RSAC Register MSB RSAC Register LSB RARC Register RSRC Register Average Current Register MSB Average Current Register LSB Temperature Register MSB Temperature Register LSB Voltage Register MSB, VIN1 - VSS Voltage Register LSB, VIN1 - VSS Current Register MSB Current Register LSB Accumulated Current Register MSB Accumulated Current Register LSB Accumulated Current Register LSB - 1 DESCRIPTION READ/WRITE R/W R/W R R R R R R R R R R R R R R R/W* R/W* R
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Table 9. Memory Map (continued)
ADDRESS (HEX) 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h to 2Fh 30h to 5Fh 60h to 80h 81h to AFh B0h B1h B2h to FDh FEh Age Scalar Register Special Feature Register Full Register MSB Full Register LSB Active-Empty Register MSB Active-Empty Register LSB Standby-Empty Register MSB Standby-Empty Register LSB Voltage Register MSB, VIN2 - VIN1 Voltage Register LSB, VIN2 - VIN1 Cycle Counter Register EEPROM Register User EEPROM Register, Lockable, Block 0 Reserved Parameter EEPROM Register, Lockable, Block 1 Reserved Factory Gain RSGAIN Register MSB Factory Gain RSGAIN Register LSB Reserved 2-Wire Command Register DESCRIPTION Accumulated Current Register LSB - 2 READ/WRITE R R/W* R/W R R R R R R R R R/W* R/W R/W -- R/W -- R R -- W
FFh Reserved -- *Register value is automatically saved to EEPROM during active-mode operation and recalled from EEPROM on power-up.
64-Bit Net Address (ROM ID)
Each DS2775-DS2778 has a unique, factory-programmed ROM ID that is 64 bits. The first 8 bits of the net address are the product family code (32h). The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 22).
Authentication
The DS2776/DS2778 have an authentication feature that is performed using a FIPS 180-compliant SHA-1 one-way hash algorithm on a 512-bit message block. The message block consists of a 64-bit secret, a 64-bit
challenge, and 384 bits of constant data. Optionally, the 64-bit net address replaces 64 of the 384 bits of constant data used in the hash operation. Contact Maxim for details of the message block organization. The host and the DS2776/DS2778 both calculate the result based on the mutually known secret. The result data, known as the message authentication code (MAC) or message digest, is returned by the DS2776/DS2778 for comparison to the host's result. Note that the secret is never transmitted on the bus and thus cannot be captured by observing bus traffic. Each authentication attempt is initiated by the host system by providing a 64-bit random challenge through the Write
8-BIT CRC MSb
48-BIT SERIAL NUMBER
8-BIT FAMILY CODE (32h) LSb
Figure 22. 1-Wire Net Address Format (ROM ID)
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Challenge command. The host then issues the Compute MAC or Compute MAC with ROM ID command. The MAC is computed per FIPS 180, and then returned as a 160-bit serial stream, beginning with the LSb. Table 10 summarizes SHA-1-related commands used while authenticating a battery or peripheral device. The Secret Management Function Commands section describes four additional commands for clearing, computing, and locking of the secret.
DS2775/DS2776/DS2777/DS2778
DS2776/DS2778 Authentication Commands
Write Challenge [0Ch]
This command writes the 64-bit challenge to the DS2776/DS2778. The LSB of the 64-bit data argument can begin immediately after the MSB of the command has been completed. If more than 8 bytes are written, the final value in the Challenge register is indeterminate. The Write Challenge command must be issued prior to every Compute MAC or Compute Next Secret command for reliable results.
Secret Management Function Commands
Table 11 summarizes all the secret management function commands.
Clear Secret [5Ah]
This command sets the 64-bit secret to all 0s (0000 0000 0000 0000h). The host must wait for tEEC for the DS2776/DS2778 to write the new secret value to EEPROM. See Figure 28 for command timing.
Compute MAC without ROM ID [36h]
This command initiates an SHA-1 computation without including the ROM ID in the message block. Because the ROM ID is not used, this command allows the use of a master secret and MAC response independent of the ROM ID. The DS2776/DS2778 computes the MAC in tSHA after receiving the last bit of this command. After the MAC computation is complete, the host must write eight write-zero time slots and then issue 160 read time slots to receive the 20-byte MAC. See Figure 25 for command timing.
Compute Next Secret without ROM ID [30h]
This command initiates an SHA-1 computation of the MAC and uses a portion of the resulting MAC as the next or new secret. The MAC computation is performed with the current 64-bit secret and the 64-bit challenge. Logical 1s are loaded in place of the ROM ID. The output MAC's 64 bits are used as the new secret value. The host must allow tSHA after issuing this command for the SHA calculation to complete, then wait tEEC for the DS2776/DS2778 to write the new secret value to EEPROM. See Figure 26 for command timing.
Compute MAC with ROM ID [35h]
This command is structured the same as the Compute MAC without ROM ID, except that the ROM ID is included in the message block. With the ROM ID unique to each DS2776/DS2778 included in the MAC computation, use of a unique secret in each token and a master secret in the host device is allowed. Refer to Application Note 1099: White Paper 4: Glossary of 1-Wire SHA-1 Terms for more information. See Figure 25 for command timing.
Compute Next Secret with ROM ID [33h]
This command initiates an SHA-1 computation of the MAC and uses a portion of the resulting MAC as the next or new secret. The MAC computation is performed with the current 64-bit secret, the 64-bit ROM ID, and the 64-bit challenge. The output MAC's 64 bits are used as the new secret value. The host must allow tSHA after issuing this command for the SHA calculation to complete, then wait tEEC for the DS2776/DS2778 to write
Table 10. Authentication Function Commands
COMMAND Write Challenge Compute MAC without ROM ID (and Return MAC for the DS2776 only) Compute MAC with ROM ID (and Return MAC for the DS2776 only) Read ROM ID (DS2778 only) Read MAC (DS2778 only) HEX 0Ch 36h 35h 39h 3Ah FUNCTION Writes 64-bit challenge for SHA-1 processing. Required prior to issuing Compute MAC and Compute Next Secret commands. Computes hash of the message block with logical 1s in place of the ROM ID. (Returns the 160-bit MAC for the DS2776 only.) Computes hash of the message block including the ROM ID. (Returns the 160-bit MAC for the DS2776 only.) Returns the ROM ID (DS2778 only). Returns the 160-bit MAC (DS2778 only).
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Table 11. Secret Management Function Commands
COMMAND Clear Secret Compute Next Secret without ROM ID Compute Next Secret with ROM ID Lock Secret HEX 5Ah 30h 33h 60h Generates new global secret. Generates new unique secret. Sets lock bit to prevent changes to the secret. FUNCTION Clears the 64-bit secret to 0000 0000 0000 0000h.
the new secret value to EEPROM. See Figure 26 for command timing.
Lock Secret [60h]
This command write protects the 64-bit secret to prevent accidental or malicious overwrite of the secret value. The secret value stored in EEPROM becomes "final." The host must wait tEEC for the DS2776/DS2778 to write the lock secret bit to EEPROM. See Figure 28 for command timing.
1-Wire Bus System (DS2775/DS2776 Only)
The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-Wire bus with multiple slaves, while a single-drop bus has only one slave device. In all instances, the DS2775/ DS2776 are slave devices. The bus master is typically a microprocessor in the host system. The discussion of this bus system consists of five topics: 64-bit net address, CRC generation, hardware configuration, transaction sequence, and 1-Wire signaling.
The host system is responsible for verifying the CRC value and taking action as a result. The DS2775/ DS2776 do not compare CRC values and do not prevent a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result in a communication channel with a very high level of integrity. The CRC can be generated by the host using a circuit consisting of a Shift register and XOR gates as shown in Figure 23, or it can be generated in software using the polynomial X8 + X5 + X4 + 1. Additional information about the Maxim 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton(R) Products. In the circuit in Figure 23, the Shift register bits are initialized to 0. Then, starting with the LSb of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the Shift register contains the CRC value. During some command sequences, the DS2775/ DS2776 also generate an 8-bit CRC and provide this value to the bus master to facilitate validation for the transfer of command, address, and data from the bus master to the DS2775/DS2776. The DS2775/DS2776 compute an 8-bit CRC for the command and address bytes received from the bus master for the Read Memory, Read Status, and Read/Generate CRC commands to confirm that these bytes have been received correctly. The CRC generator on the DS2775/DS2776 is
CRC Generation
The DS2775/DS2776 have an 8-bit CRC stored in the MSB of its 64-bit net address and generates a CRC during some command protocols. To ensure error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of the address and compare it to the CRC from the DS2775/DS2776.
INPUT MSb XOR XOR LSb
XOR
Figure 23. 1-Wire CRC Generation Block Diagram iButton is a registered trademark of Maxim Integrated Products, Inc.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
also used to provide verification of error-free data transfer as each EEPROM page is sent to the master during a Read Data/Generate CRC command and for the 8 bytes of information in the status memory field. In each case where a CRC is used for data transfer validation, the bus master must calculate the CRC value using the same polynomial function and compare the calculated value to the CRC either stored in the DS2775/DS2776 net address or computed by the DS2775/DS2776. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry in the DS2775/DS2776 that prevents a command sequence from proceeding if the stored or calculated CRC from the DS2775/DS2776 and the calculated CRC from the host do not match. the low period as a reset pulse, effectively terminating the transaction.
DS2775/DS2776/DS2777/DS2778
Transaction Sequence
The protocol for accessing the DS2775/DS2776 through the 1-Wire port is as follows: * * * * Initialization Net Address Commands Function Command(s) Data Transfer (not all commands have data transfer)
Initialization
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the bus master, followed by a presence pulse simultaneously transmitted by the DS2775/DS2776 and any other slaves on the bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For more details, see the 1-Wire Signaling section.
Hardware Configuration
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain or three-state output drivers. The DS2775/ DS2776 use an open-drain output driver as part of the bidirectional interface circuitry shown in Figure 24. If a bidirectional pin is not available on the bus master, separate output and input pins can be connected together. The 1-Wire bus must have a pullup resistor at the bus master end. A value of between 2k and 5k is recommended. The idle state for the 1-Wire bus is high. If, for any reason, a bus transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. Note that if the bus is left low for more than tLOW0, slave devices on the bus begin to interpret
Net Address Commands
Once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following sections. The name of each Net Address command (ROM command) is followed by the 8-bit op code for that command in square brackets.
Read Net Address [33h] This command allows the bus master to read the DS2775/DS2776's 1-Wire net address. This command can only be used if there is a single slave on the bus. If more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result).
VPULLUP (2.0V TO 5.5V) BUS MASTER 4.7k Rx 100nA (TYP) 100 MOSFET Rx DS2775/DS2776 1-Wire PORT (DQ)
Tx Rx = RECEIVE Tx = TRANSMIT
Tx
Figure 24. 1-Wire Bus Interface Circuitry
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Match Net Address [55h] This command allows the bus master to specifically address one DS2775/DS2776 on the 1-Wire bus. Only the addressed DS2775/DS2776 responds to any subsequent function command. All other slave devices ignore the function command and wait for a reset pulse. This command can be used with one or more slave devices on the bus. Skip Net Address [CCh] This command saves time when there is only one DS2775/DS2776 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. If more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. Search Net Address [F0h] This command allows the bus master to use a process of elimination to identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple three-step routine on each bit location of the net address. After one complete pass through all 64 bits, the bus master knows the address of one device. The remaining devices can then be identified on additional iterations of the process. See Chapter 5 in Application Note 937: Book of iButton Standards for a comprehensive discussion of a net address search, including an actual example.
ing at memory address 00h and the address is automatically incremented until a reset pulse occurs. Addresses labeled Reserved in the Memory Map contain undefined data values (see Table 9). The Read Data command can be terminated by the bus master with a reset pulse at any bit boundary. Reads from EEPROM block addresses return the data in the shadow RAM. A Recall Data command is required to transfer data from the EEPROM to the shadow. See the Memory section for more details.
Write Data [6Ch, XXh] This command writes data to the DS2775/DS2776 starting at memory address XXh. The LSb of the data to be stored at address XXh can be written immediately after the MSb of the address has been entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb to be stored at address XXh + 1 can be written immediately after the MSb to be stored at address XXh. If the bus master continues to write beyond address FFh, the data starting at address 00 is overwritten. Writes to read-only addresses, reserved addresses, and locked EEPROM blocks are ignored. Incomplete bytes are not written. Writes to unlocked EEPROM block addresses modify the shadow RAM. A Copy Data command is required to transfer data from the shadow to the EEPROM. See the Memory section for more details. Copy Data [48h, XXh] This command copies the contents of the EEPROM shadow RAM to EEPROM cells for the EEPROM block containing address XXh. Copy Data commands that address locked blocks are ignored. While the Copy Data command is executing, the EEC bit in the EEPROM register is set to 1 and writes to EEPROM addresses are ignored. Reads and writes to non-EEPROM addresses can still occur while the copy is in progress. The Copy Data command takes tEEC time to execute, starting on the next falling edge after the address is transmitted. See Figure 27 for more information. Recall Data [B8h, XXh] This command recalls the contents of the EEPROM cells to the EEPROM shadow memory for the EEPROM block containing address XXh. Lock [6Ah, XXh] This command locks (write protects) the block of EEPROM memory containing memory address XXh. The LOCK bit in the EEPROM register must be set to 1 before the Lock command is executed. To help prevent unintentional locks, one must issue the Lock command immediately after setting the LOCK bit (EEPROM
Function Commands
After successfully completing one of the net address commands, the bus master can access the features of the DS2775/DS2776 with any of the function commands described in the following paragraphs. The name of each function is followed by the 8-bit op code for that command in square brackets. The function commands are summarized in Table 12. Table 13 details the requirements for using the function commands.
Read Data [69h, XXh] This command reads data from the DS2775/DS2776 starting at memory address XXh. The LSb of the data in address XXh is available to be read immediately after the MSb of the address has been entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XXh + 1 is available to be read immediately after the MSb of the data at address XXh. If the bus master continues to read beyond address FFh, data is read start36
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
register, address 1Fh, bit 6) to a 1. If the LOCK bit is 0 or if setting the LOCK bit to 1 does not immediately precede the Lock command, the Lock command has no effect. The Lock command is permanent; a locked block can never be written again.
DS2775/DS2776/DS2777/DS2778
Table 12. All Function Commands
COMMAND Write Challenge Compute MAC without ROM ID (and Return MAC for the DS2776 only) Compute MAC with ROM ID (and Return MAC for the DS2776 only) Clear Secret Compute Next Secret without the ROM ID Compute Next Secret with ROM ID Read ROM ID (DS2778 only) Read MAC (DS2778 only) Lock Secret Read Data Write Data Copy Data Recall Data Lock Reset HEX 0Ch 36h 35h 5Ah 30h 33h 39h 3Ah 60h DESCRIPTION Writes 64-bit challenge for SHA-1 processing. Required immediately prior to all Compute MAC and Compute Next Secret commands. Computes hash of the message block with logical 1s in place of ROM ID. (Returns the 160-bit MAC for the DS2776 only.) Computes hash of the message block using the ROM ID. (Returns the 160-bit MAC for the DS2776 only.) Clears the 64-bit secret to 0000 0000 0000 0000h. Generates new global secret. Generates new unique secret. Returns the ROM ID (DS2778 only). Returns the 160-bit MAC (DS2778 only). Sets lock bit to prevent changes to the secret.
69h, XXh Reads data from memory starting at address XXh. 6Ch, XXh Writes data to memory starting at address XXh. 48h, XXh Copies shadow RAM data to EEPROM block containing address XXh. B8h, XXh Recalls EEPROM block containing address XXh to RAM. 6Ah, XXh Permanently locks the block of EEPROM containing address XXh. BBh Resets DS2775/DS2776 (software POR).
Table 13. Guide to Function Command Requirements
COMMAND Write Challenge Compute MAC Compute Next Secret Clear/Lock Secret, Set/Clear Read Data Write Data Copy Data Recall Data Lock Reset ISSUE MEMORY ADDRESS (BITS) -- -- -- -- 8 8 8 8 8 -- ISSUE 00h BEFORE READ -- Yes -- -- -- -- -- -- -- -- READ/WRITE TIME SLOTS Write: 64 Read: Up to 160 -- -- Read: Up to 2048 Write: Up to 2048 -- -- -- --
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37
2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
tSHA
1-Wire RESET
SKIP-ROM COMMAND COMPUTE MAC COMMAND
WAIT FOR MAC COMPUTATION 8 WRITE-ZERO TIME SLOTS
UP TO 160 READ TIME SLOTS (READ 20-BYTE MAC)
PRESENCE PULSE
Figure 25. Compute MAC Command
tSHA
tEEC
1-Wire RESET
SKIP-ROM COMMAND COMPUTE NEXT SECRET COMMAND
WAIT FOR MAC COMPUTATION
WAIT FOR EEPROM PROGRAMMING
PRESENCE PULSE
Figure 26. Compute Next Secret Command
tEEC
1-Wire RESET
SKIP-ROM COMMAND
COPY DATA COMMAND
8 WRITE TIME SLOTS
WAIT FOR EEPROM PROGRAMMING
PRESENCE PULSE
Figure 27. Copy Data Command
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
tEEC
1-Wire RESET
SKIP-ROM COMMAND
CLEAR/LOCK SECRET COMMAND OR SET/CLEAR OVERDRIVE COMMAND
WAIT FOR EEPROM COPY TIME
PRESENCE PULSE
Figure 28. Clear/Lock Secret, Set/Clear Overdrive Commands
tRSTL
tRSTH
tPDH
tPDL PK+
DQ PK-
LINE TYPE LEGEND: BUS MASTER ACTIVE LOW RESISTOR PULLUP DS2775/DS2776 ACTIVE LOW
Figure 29. 1-Wire Initialization Sequence
1-Wire Signaling
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the DS2775/DS2776 are as follows: the initialization sequence (reset pulse followed by presence pulse), write-zero, write-one, and read data. The bus master initiates all these types of signaling except the presence pulse.
Figure 29 shows the initialization sequence required to begin any communication with the DS2775/DS2776. A presence pulse following a reset pulse indicates that the DS2775/DS2776 are ready to accept a Net Address command. The bus master transmits (Tx) a reset pulse for tRSTL. The bus master then releases the line and goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin, the DS2775/DS2776 wait for tPDH and then transmit the presence pulse for tPDL.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Write Time Slots
A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low level. There are two types of write time slots: write-one and write-zero. All write time slots must be tSLOT in duration with a 1s minimum recovery time, tREC, between cycles. The DS2775/DS2776 sample the 1-Wire bus line between tLOW1_MAX and tLOW0_MIN after the line falls. If the line is high when sampled, a write-one occurs. If the line is low when sampled, a write-zero occurs. Figure 30 illustrates the sample window. For the bus master to generate a write-one time slot, the bus line must be pulled low and then released, allowing the line to be pulled high less than tRDV after the start of the write time slot. For the host to generate a write-zero time slot, the bus line must be pulled low and held low for the duration of the write time slot. trol of a master device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and STOP bits which begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock cycle with the cycle defined by SCL transitioning low-to-high and then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any change in SDA when SCL is high is interpreted as a START (S) or STOP (P) control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.
Read Time Slots
A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level. The bus master must keep the bus line low for at least 1s and then release it to allow the DS2775/ DS2776 to present valid data. The bus master can then sample the data tRDV from the start of the read time slot. By the end of the read time slot, the DS2775/DS2776 release the bus line and allow it to be pulled high by the external pullup resistor. All read time slots must be tSLOT in duration with a 1s minimum recovery time, tREC, between cycles. See Figure 30 and the timing specifications in the Electrical Characteristics: 1-Wire Interface, Standard/Overdrive tables for more information.
START and STOP Conditions
The master initiates transactions with a START condition by forcing a high-to-low transition on SDA while SCL is high. The master terminates a transaction with a STOP condition, a low-to-high transition on SDA while SCL is high. A repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one transaction and begin another without returning the bus to the idle state. In multimaster systems, a repeated START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities in which the SDA transitions when SCL is high.
2-Wire Bus System
The 2-wire bus system supports operation as a slaveonly device in a single or multislave and single or multimaster system. Up to 128 slave devices can share the bus by uniquely setting the 7-bit slave address. The 2-wire interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional communication between the DS2777/DS2778 slave device and a master device at speeds up to 400kHz. The DS2777/DS2778's SDA pin operates bidirectionally, that is, when the DS2777/DS2778 receive data, SDA operates as an input, and when the DS2777/DS2778 return data, SDA operates as an opendrain output with the host system providing a resistive pullup. The DS2777/DS2778 always operate as a slave device, receiving and transmitting data under the con-
Acknowledge Bits
Each byte of a data transfer is acknowledged with an acknowledge bit (A) or a not acknowledge bit (N). Both the master and the DS2777/DS2778 slave generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (9th pulse) and keep it low until SCL returns low. To generate a not acknowledge (also called NACK), the receiver releases SDA before the rising edge of the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
WRITE-ZERO SLOT tSLOT tLOW0 tREC VPULLUP tLOW1 WRITE-ONE SLOT tSLOT
GND DEVICE SAMPLE WINDOW MIN TYP MAX MODE: STANDARD 15s 15s 30s 15s 15s 30s > 1s MIN DEVICE SAMPLE WINDOW TYP MAX
OVERDRIVE
2s
1s
3s
2s
1s
3s
READ-ZERO SLOT tSLOT VPULLUP tRDV tREC
READ-ONE SLOT tSLOT tRDV
GND > 1s MASTER SAMPLE WINDOW MODE: STANDARD OVERDRIVE 15s 2s 15s 2s MASTER SAMPLE WINDOW
LINE TYPE LEGEND: BUS MASTER ACTIVE LOW BOTH BUS MASTER AND SLAVE ACTIVE LOW SLAVE ACTIVE LOW RESISTOR PULLUP
Figure 30. 1-Wire Write and Read Time Slots
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Data Order
A byte of data consists of 8 bits ordered MSb first. The LSb of each byte is followed by the acknowledge bit. The DS2777/DS2778 registers composed of multibyte values are ordered MSB first. The MSB of multibyte registers is stored on even data memory addresses. selects a read transaction, with the subsequent bytes being read from the slave by the master.
Bus Timing
The DS2777/DS2778 are compatible with any bus timing up to 400kHz. No special configuration is required to operate at any speed.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by a slave address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2777/DS2778 continuously monitor for a START condition followed by its slave address. When the DS2777/DS2778 receive a slave address that matches the value in its Programmable Slave Address register, they respond with an acknowledge bit during the clock period following the R/W bit. The 7-bit Programmable Slave Address register is factory programmed to 1011001. The slave address can be reprogrammed. See the Programmable Slave Address section for details.
2-Wire Command Protocols
The command protocols involve several transaction formats. The simplest format consists of the master writing the START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2777/DS2778. More complex formats such as the Write Data, Read Data, and function command protocols write data, read data, and execute device-specific operations. All bytes in each command format require the slave or host to return an acknowledge bit before continuing with the next byte. Each function command definition outlines the required transaction format. Table 14 applies to the transaction formats.
Programmable Slave Address
The 2-wire slave address of the DS2777/DS2778 is stored in the parameter EEPROM block, address 80h. Programming the slave address requires a write to 80h with the desired slave address. The new slave address value is effective following the write to 80h and must be used to address the DS2777/DS2778 on subsequent bus transactions. The slave address value is not stored to EEPROM until a Copy EEPROM Block 1 command is executed. Prior to executing the Copy Data command, power cycling the DS2777/DS2778 restores the original slave address value. The data format of the slave address value in address 80h is shown in the Slave Address Format (80h) section.
Basic Transaction Formats
Write: S SAddr W A MAddr A Data0 A P A write transaction transfers one or more data bytes to the DS2777/DS2778. The data transfer begins at the memory address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the transaction, except for the acknowledge cycles.
Read: S SAddr W A MAddr A Sr SAddr R A Data0 N P Write Portion Read Portion
Read/Write Bit
The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0 selects a write transaction, with the subsequent bytes being written by the master to the slave. R/W = 1
A read transaction transfers one or more bytes from the DS2777/DS2778. Read transactions are composed of two parts with a write portion followed by a read portion and are, therefore, inherently longer than a write transaction. The write portion communicates the starting point for the read operation. The read portion follows immediately, beginning with a repeated START, and slave address with R/W set to a 1. Control of SDA is
Slave Address Format (80h)
BIT 7 A6 BIT 6 A5 BIT 5 A4 BIT 4 A3 BIT 3 A2 BIT 2 A1 BIT 1 A0 BIT 0 X
Bits 7 to 1: Slave Address (A[6:0]). A[6:0] contains the 7-bit slave address of the DS2777/DS2778. The factory default is 1011001b. Bit 0: Reserved.
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Table 14. 2-Wire Protocol Key
KEY S SAddr FCmd MAddr Data A N DESCRIPTION START Bit Slave Address (7-bit) Function Command Byte Memory Address Byte Data Byte Written by Master Acknowledge Bit (Master) Not Acknowledge (Master) KEY Sr W R P Data A N DESCRIPTION Repeated START R/W Bit = 0 R/W Bit = 1 STOP bit Data Byte Returned by Slave Acknowledge Bit (Slave) Not Acknowledge (Slave)
DS2775/DS2776/DS2777/DS2778
assumed by the DS2777/DS2778 beginning with the slave address acknowledge cycle. Control of the SDA signal is retained by the DS2777/DS2778 throughout the transaction, except for the acknowledge cycles. The master indicates the end of a read transaction by responding to the last byte it requires with a no acknowledge. This signals the DS2777/DS2778 that control of SDA is to remain with the master following the acknowledge clock.
Read-Data Protocol
The read-data protocol is used to read register and shadow RAM data from the DS2777/DS2778 starting at a memory address specified by MAddr. Data0 represents the data byte in memory location MAddr, Data1 represents the data from MAddr + 1, and DataN represents the last byte read by the master. S SAddr W A MAddr A Sr SAddr R A Data0 A Data1 A ... DataN N P Data is returned beginning with the MSb of the data in MAddr. Because the address is automatically incremented after the LSb of each byte is returned, the MSb of the data at address MAddr + 1 is available to the host immediately after the acknowledgement of the data at address MAddr. If the bus master continues to read beyond address FFh, the DS2777/DS2778 output data values of FFh. Addresses labeled reserved in the Memory Map return undefined data. The bus master terminates the read transaction at any byte boundary by issuing a not acknowledge followed by a STOP or repeated START.
Write-Data Protocol
The write-data protocol is used to write to register and shadow RAM data to the DS2777/DS2778 starting at memory address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1 and DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by sending a STOP or repeated START after receiving the last acknowledge bit. S SAddr W A MAddr A Data0 A Data1 A ... DataN A P The MSb of the data to be stored at address MAddr can be written immediately after the MAddr byte is acknowledged. Because the address is automatically incremented after the LSb of each byte is received by the DS2777/DS2778, the MSb of the data at address MAddr + 1 is written immediately after the acknowledgement of the data at address MAddr. If the bus master continues an autoincremented write transaction beyond address 4Fh, the DS2777/DS2778 ignore the data. Data is also ignored on writes to read-only addresses and reserved addresses, locked EEPROM blocks, as well as a write that auto-increments to the Function Command register (address FEh). Incomplete bytes and bytes that are not acknowledged by the DS2777/DS2778 are not written to memory. As noted in the Memory section, writes to unlocked EEPROM blocks modify the shadow RAM only.
Function Command Protocol
The function command protocol executes a devicespecific operation by writing one of the function command values (FCmd) to memory address FEh. Table 15 lists the DS2777/DS2778 FCmd values and describes the actions taken by each. A 1-byte write protocol is used to transmit the function command, with the MAddr set to FEh and the data byte set to the desired FCmd value. Additional data bytes are ignored. Data read from memory address FEh is undefined. S SAddr W A MAddr = 0FEh A FCmd A P
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication DS2775/DS2776/DS2777/DS2778
Table 15. Function Commands
FUNCTION COMMAND TARGET EEPROM BLOCK FCmd VALUE DESCRIPTION This command copies the shadow RAM to the target EEPROM block. Copy data commands that target locked blocks are ignored. While the Copy Data command is executing, the EEC bit in the EEPROM register is set to 1, and write data commands with MAddr set to any address within the target block are ignored. Read data and write data commands with MAddr set outside the target block are processed while the copy is in progress. The Copy Data command execution time, tEEC, is 2ms typical and starts after the FCmd byte is acknowledged. Subsequent copy or lock commands must be delayed until the EEPROM programming cycle completes. This command recalls the contents of the targeted EEPROM block to its shadow RAM. This command locks (write protects) the targeted EEPROM block. The LOCK bit in the EEPROM register must be set to 1 before the Lock command is executed. If the LOCK bit is 0, the Lock command has no effect. The Lock command is permanent; a locked block can never be written again. The Lock command execution time, t EEC, is 2ms typical and starts after the FCmd byte is acknowledged. Subsequent copy or lock commands must be delayed until the EEPROM programming cycle completes. This command initiates a read of the unique 64-bit ROM ID. After the Read ROM ID command is sent, the ROM ID can be read with the following sequence: S SAddr R Data0 A Data1 A ... Data7 N P
0 Copy Data 1
42h
44h
Recall Data
0 1 0
B2h B4h 63h
Lock 1 66h
Read ROM ID
--
39h
Selector Guide
PART DS2775G+ DS2775G+T&R DS2776G+ DS2776G+T&R DS2777G+ DS2777G+T&R DS2778G+ DS2778G+T&R INTERFACE 1-Wire 1-Wire 1-Wire 1-Wire 2-Wire 2-Wire 2-Wire 2-Wire SHA-1 No No Yes Yes No No Yes Yes
Pin Configuration
TOP VIEW
CC VDD DC VIN2 VIN1 VB VSS 1 2 3 4 5 6 7
+
DS2775 DS2776 DS2777 DS2778 *EP
14 13 12 11 10 9 8
CP SRC SCL/OVD SDA/DQ PLS PIO SNS
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel.
TDFN-EP (3mm x 5mm)
*EXPOSED PAD
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 14 TDFN PACKAGE CODE T1435+1 DOCUMENT NO. 21-0253
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2-Cell, Stand-Alone, Li+ Fuel-Gauge IC with Protector and Optional SHA-1 Authentication
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 10/08 3/09 7/09 Initial release. Corrected values in the VOV Register Programmability table (Table 5). Corrected the 2-wire slave address default value to 1011001. DESCRIPTION PAGES CHANGED -- 27 42
DS2775/DS2776/DS2777/DS2778
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 45
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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